Pipeline analog-to-digital converters (ADCs) are used in many devices including communication devices such as Ethernet switches, routers, access points, and mobile communication devices (e.g., cell phones, tablets, personal data assistants (PDAs), etc.). A pipeline ADC may include multiple ADC stages coupled in series, each contributing a number of bits, and a final flash ADC. The bits generated by the ADC stages and the flash ADC are time aligned and digitally corrected for any errors before being encoded by an encoder.
Each stage of the pipeline ADC includes a sample-and-hold (S&H), a flash ADC, a digital-to-analog converter (DAC) such as a multiplying DAC (MDAC), a combiner, and a residue amplifier. In each stage, the S&H samples the input signal and holds the signal steady while the flash ADC quantizes the input signal to a number of bits that form output bits of the stage. Meanwhile, the MDAC converts the output bits of the stage back to an analog signal that is subtracted, using the combiner, from the held sample of the input signal to generate a residue signal. The residue signal is amplified by the residue amplifier and passed to the next stage of the pipeline ADC. In order for the pipeline ADC to achieve a high accuracy, the residue amplifier has to have an accurate gain, which results in a larger area and a higher power consumption and cost. A lower cost and more power efficient method of maintaining the gain is through gain calibration of the residue amplifier.